Si (silicon) field-effect transistors that are used mainly in current semiconductor devices are of a normally-off type. A normally-off field-effect transistor is a transistor that is conducting in the presence of the application of a positive voltage between a gate electrode (G) and a source electrode (S) and is nonconducting in the absence of the application of a positive voltage between the gate electrode (G) and the source electrode (S). One way of achieving this normally-off field-effect transistor is a lateral double-diffused MOS field-effect transistor (LDMOSFET). This lateral double-diffused MOS field-effect transistor has such a feature that a source electrode (S) and a drain electrode (D) are formed on the same surface of a semiconductor substrate and, furthermore, such a feature that a connection to an electrode located on the back of a semiconductor can be made by a trench passing from the source electrode (S) through the semiconductor.
Meanwhile, III-N field-effect transistors, such as GaN field-effect transistors, which have been being studied from a practical application standpoint because of their high-withstand-voltage, low-loss, fast-switching, high-temperature operation, and similar features are of a normally-on type. A normally-on field-effect transistor has a negative threshold voltage, is nonconducting in a case where a voltage between a gate electrode (G) and a source electrode (S) is lower than the threshold voltage, and is conducting in a case where the voltage between the gate electrode (G) and the source electrode (S) is higher than the threshold voltage. Use of such a normally-on field-effect transistor in a semiconductor device creates various problems such as unserviceability of a conventional gate drive circuit.
To address these problems, PTL 1, listed below, proposes configuring a normally-off composite semiconductor device by serially connecting a normally-on field-effect transistor and a normally-off field-effect transistor. Further, PTL 2, listed below, proposes a method for, in order to prevent a normally-off field-effect transistor from being broken down by an increase in voltage between a drain electrode (D) and a source electrode (S) of the normally-off field-effect transistor, restricting the voltage between the drain electrode (D) and the source electrode (S) to not higher than the withstand voltage of the normally-off field-effect transistor by connecting a Zener diode between the drain electrode (D) and the source electrode (S) of the normally-off field-effect transistor. PTL 3, listed below, proposes a method for lowering gate resistance by making a connection to a gate-electrode-shunting substrate wire. PTL 4, listed below, describes a configuration in which the offset drain region of a power MOSFET, disposed in between a gate electrode and an n+-type drain region, has a dual offset structure so that both on resistance (Ron) and feedback capacitance (Cgd) are reduced. PTL 5, listed below, describes a method for reducing the resistance of a gate wire by suppressing an increase in wiring resistance of a source and a drain. PTL 6, listed below, describes a configuration in which a gate interconnection pattern is improved so that the number of effective cells is increased by effectively utilizing a chip area or the chip area is reduced.